The present invention relates to double-gated field effect transistors (FETs), and in particular to a process of fabricating double-gated FETs wherein a damascene-like replacement gate processing step is employed to create sidewall source/drain regions, oxide spacers and gate structures inside a previously formed trench.
In order to make integrated circuits (ICs) such as memory, logic and other devices, of higher integration density than currently feasible, one has to find a means to further scale down the FET devices that are present therein. Moreover, as FET dimensions are scaled down, it becomes increasingly difficult to control short-channel effects by conventional means. Short-channel effects, as well known to those skilled in the art, are the decrease in threshold voltage, V1, in short-channel devices, i.e., sub-0.1 micron, due to two-dimensional electrostatic charge sharing between the gate and the source/drain regions.
An evolution beyond the standard single gate metal oxide semiconductor field effect transistor (MOSFET) is the double-gate MOSFET, where the device channel is confined between top and bottom gate dielectric layers. This structure, with a symmetrical gate structure, can be scaled to about half of the channel length as compared to a conventional single gate MOSFET structure. It is well known that a dual gate or double gate MOSFET device has several advantages over conventional single gate MOSFET devices. Specifically, the advantages for dual gate MOSFET devices over their single gate counterparts include: a higher transconductance, lower parasitic capacitance, and improved short-channel effects. For instance, Monte-Carlo simulation has been previously carried out on a 30 nm channel dual gate MOSFET device and has shown that the dual gate device has a very high transconductance (2300 mS/mm) and fast switching speeds (1.1 ps for nMOSFET).
Moreover, improved short-channel characteristics are obtained down to 20 nm channel length with no doping needed in the channel region. This circumvents all the tunneling breakdown, dopant quantization, and dopant depletion problems associated with channel doping that are normally present with single gate MOSFET devices.
Some examples of prior art double-gate MOSFETs are found in the following references:
U.S. Pat. No. 5,188,973 describes a double-gate structure in which the bottom gate is not self-aligned to the top gate. This prior art double-gate structure is quite different from the double-gate structure described herein in that the inventive double-gate structure contains self-aligned bottom and top gates. Moreover, the process and design philosophy is very different from the one presented hereinbelow.
U.S. Pat. No. 5,140,391 describes another double-gate structure. In this prior art double-gate structure, no sidewall source and drain regions are disclosed. Moreover, in the ""391 patent, the bottom gate of the transistor is patterned before the channel region is grown and the disclosed transistor does not contain self-aligned top and bottom gates.
U.S. Pat. No. 5,349,228 describes another double-gate structure in which no sidewall source/drain regions are disclosed. Additionally, in the ""228 patent, the bottom gate has to be oxidized. The use of such oxidation greatly limits the choice of bottom gate materials. Furthermore, in the ""228 patent, the bottom gate oxide has to be formed before the channel which precludes the use of high-quality grown silicon/silicon dioxide interfaces from the bottom oxide.
To date, prior art methods for fabricating double-gate MOSFETs have either been very complex or have severe drawbacks in terms of parameter control. Moreover, some of the structures known in the art have large parasitic capacitance to the bottom gate.
Co-assigned U.S. Pat. No. 5,773,331 describes a structure and method for fabricating a double-gate MOSFET structure in which the above problems have been solved. In particular, the ""331 patent describes a double-gate MOSFET having sidewall source and drain contacts and bottom and top gate oxides that are self-aligned. The structure disclosed in the ""331 patent has low parasitic capacitance to the bottom gate and a reduced drain and source resistance as compared to other prior art double-gate MOSFETs.
In the ""331 patent, the double-gate MOSFET having the above-mentioned characteristics is obtained by the steps of: forming a channel layer; forming a top gate insulator layer on said channel layer; forming a top gate on said top gate insulator; forming a gate pillar on the top gate; forming insulating sidewall layers adjacent to said top gate and said gate pillar; forming an integral source/drain region within said channel layer by introduction of dopants; forming conductive amorphous sidewalls on either side of, and adjacent to said insulating sidewall layers, one of said amorphous silicon sidewalls being connected to said drain region and one being connected to said source region; and etching said channel layer using said top gate, gate pillar, insulating sidewall layers and amorphous silicon sidewalls as a mask, thereby transferring the lateral extension of said mask into said channel layer, providing for a channel with integral source/drain regions being raised with respect to the support structure
The present application provides an alternative means for fabricating a double-gate MOSFET structure having properties that are essentially the same as those disclosed in the ""331 patent.
One object of the present invention is to provide a process of fabricating a dense double-gated field effect transistor (FET) wherein the gate length of the transistor is much smaller than the lithographic line.
Another object of the present invention is to provide a process of fabricating a double-gated FET having an inside-out geometry which enables the formation of a tapered body region with a thicker body under the contacts thereby reducing access resistance.
A further object of the present invention is to provide a process of fabricating a double-gated FET in which threshold voltage roll-off has been essentially reduced.
A still further object of the present invention is to provide a process of fabricating a double-gated FET which is compatible with current IC fabrication techniques.
An even further object of the present invention is to provide a process of fabricating a double-gated FET having low-parasitic capacitance to the bottom gate and a reduced source and drain resistance.
A still even further object of the present invention is to provide a process of fabricating a double-gated FET where the bottom and top gates are self-aligned.
These and other objects and advantages are achieved in the present invention by utilizing a damascene-like replacement gate process to create sidewall source/drain regions, oxide spacers and a gate structure in a previously formed trench. Multiple chemical-mechanical polishing (CMP) steps are also employed in the inventive process to square off the top of the structure at various stages of its fabrication. In accordance with the present invention, the top gate of the double-gated FET is built inside a top gate trench which contains source/drain regions and oxide spacers formed therein.
This achieves the following advantages:
(i) The inside-out geometry enables one to form a tapered body region with a thicker body under the contacts to reduce access resistance.
(ii) Since lithography defines the largest dimension, the top gate length may be much smaller than the minimum lithographic feature.
(iii) The bottom gate is referenced to the lithographic top gate stencil, resulting in better line width control.
(iv) The inventive structure has an inverted geometry with tapered sides facing one of the gates.
Specifically, the process of the present invention, which is capable of forming a double-gate FET having sidewall source and drain regions as well as sidewall silicide contacts, comprises the steps of:
providing a pad stack to a structure which comprises a Si layer present atop a backgate material stack whose bottom surface is bonded to a surface of a handle wafer, said backgate material stack includes a bottom insulator, a bottom gate electrode and a bottom gate dielectric;
forming an opening through said pad stack which extends to the bottom insulator to expose sidewalls of said Si layer and said bottom gate electrode;
protecting the exposed sidewalls of said, Si layer and recessing exposed sidewall portions of said bottom gate electrode;
planarizing the structure and forming a material stack having a top gate trench opening therein;
forming sidewall source and drain regions on exposed sidewalls of said top gate trench;
forming a top gate between said sidewall source and drain regions, said top gate being protected with a top gate protect insulator;
etching source and drain wells, self-aligned to said top gate and said sidewall source and drain regions;
forming source and drain well implants regions in preselective portions of the structure;
etching said bottom gate through said source and drain wells so as to be self-aligned to sidewall source and drain structures and hence to the top gate;
protecting exposed sidewalls of said bottom gate; and
forming source and drain contacts and contact plugs.
In addition to the above processing steps, the present invention also provides a novel double-gated FET structure which has an inside-out geometry that enables one to form a tapered body region with a thicker body under contacts to reduce access resistance. Specifically, the inventive double-gated FET comprises:
a top gate and a bottom gate which are separated by two gate dielectric layers which are sandwiched between a device channel region, said top and bottom gates are self-aligned with each other;
sidewall source and drain regions that are located in regions that are adjacent and between said top and bottom gates;
silicide gate contacts which are in electrical contact with said top and bottom gates and are located adjacent to said source and drain regions; and
source and drain wells that are located in regions abutting the silicide gate contacts.